1. Technical Field
The present invention relates generally to semiconductor manufacturing and, more particularly, to a method of making oxide and multiple thickness oxide with masked laser oxidation.
2. Related Art
Heretofore, many high performance chips have required more than one gate oxide thickness for MOSFET devices on a chip to optimize the internal circuits which operate at lower voltages and input/output (I/O) circuits which operate at high voltages. Further, the competition for improved circuit performance has driven the device channel scaling down to 0.18 um or shorter to obtain higher current drive from CMOS devices. Gate oxide has been scaled below 5 nm to keep a strong gate control of the device to minimize the short channel effects. The devices operate at 2.5 volt or below in order to maintain the high reliability. Since many other components on the board or in the system still operate at 3.3V or 5V, the input/output circuits of the chip must receive and drive 3.3V or 5V signals. As a result, oxide in these circuits are stressed at higher electrical fields than in the internal logic circuit during product operation, thus degrading chip reliability.
Prior to the present invention, the provision of gate silicon oxide in differing thicknesses has been generally provided through multiple oxidation processes with etching of the first oxide followed by a growth of a thinner oxide layer with a photoresist over the oxide area where thicker oxide is formed. Another process provides a single oxidation process with partial etching of oxide to make thinner oxide with a photoresist on the oxide where thicker oxide is desired. Unfortunately, photoresist processes and the subsequent cleaning processes have been known as a major source of oxide defects in the prior art. A further disadvantage of the prior art method is the complexity of the process in requiring a photolithography and etch.
Another disadvantage of the prior art method is that either a furnace oxidation or rapid thermal oxidation heats up a whole wafer, thus the doping, particularly the channel tailor doping of the high performance device with thinner gate oxide, is moved significantly during the multiple oxidation steps, resulting in the poor device parametric controls and performance degradation.
From above, there is a need for a new method of creating different thickness gate oxide to provide for the differing voltages used within a chip.